The invention relates to semiconductor manufacturing processes, and more particularly to a method of making field effect transistors having source and drain regions self-aligned to the gates thereof.
In fabrication of complementary metal oxide semiconductor (CMOS) integrated circuits, gate sidewall spacers are sometimes used to control the spacing between the source and drain regions of field effect transistors (FETs) and the gates of the FETs. Typically in such process, source and drain doping is performed by ion implantation into a semiconductor substrate, using the gate stack and one or more spacers formed on sidewalls of the gate stack as a mask.
Many integrated circuits (“ICs” or “chips”) include both n-type FETs (NFETs) and p-type FETs (PFETs), such as integrated circuits having complementary metal oxide semiconductor (CMOS) technology, but non-CMOS technology chips such as NMOS chips often incorporate PFETs as well. For best performance, it is sometimes desirable or necessary for the source and drain regions of a PFET to be spaced a different distance from the gate of the PFET than is the case for an NFET on the same chip. The source and drain regions may either be spaced farther away from the gate in the PFET than in the NFET or, alternatively, closer to the gate.
In a particular instance, it is desirable to space the source and drain regions farther away from the channel in the PFET than in the NFET (and hence farther from the gate of the PFET) because of a silicide which is provided on the source and drain regions of the PFET and NFET. When particular types of silicide are used such as CoSi2, the silicide has a tendency during processing of the chip to draw the dopant boron out of the PFET by migration. Boron is drawn from the source and drain regions of the PFET where it is the primary dopant, and in turn, from the channel region where it is also generally provided for other purposes such as for threshold adjustment. As a result, the boron concentration at locations in the channel region of the PFET can fall below a desirable level. To reduce this effect to a tolerable level, the source and drain regions of the PFET should be located at a sufficient distance from the channel. Therefore, the gate sidewall spacer or spacers used to self-align the source and drain regions in the PFET to the channel should be relatively thick.
However, if spacers of the same thickness are used to self-align the source and drain regions in the NFET, less than desirable performance results. Since the problem of boron migration is not suffered by the NFET, the gate sidewall spacer need not be as thick. Better performance is achieved when the source and drain regions of the NFET are spaced more closely to the channel of the NFET, hence the need to use a thinner gate sidewall spacer in the NFET.
It is further desirable to form both NFETs and PFETs of the chip by an integrated process in which most steps are common to both types of transistors and only a few steps are performed separately to the NFETs and the PFETs. With reference to FIG. 1A, in a technique which is background to the present invention but which is not admitted to be prior art, a gate sidewall spacer or set of spacers are patterned by wet etch processing to have different widths in respective areas where NFETs and PFETs are formed.
FIG. 1A is a top down view of a PFET 14 and an NFET 12 which share a common gate conductor 10. The PFET 14 is formed over a first active area 40 which is surrounded by an isolation 30 such as a trench isolation. The PFET has source and drain regions 50 which are spaced a distance 55 from the gate conductor 10 by a spacer or set of spacers shown at 70, hereinafter referred to as “spacer” 70. The NFET 12 is formed over a second active area 42 which is also surrounded by an isolation 30 such as a shallow trench isolation (STI). The NFET 12 has source and drain regions 60 which are spaced a distance 57 from the gate conductor 10 by a spacer or set of spacers shown at 72, hereinafter referred to as “spacer” 72.
According to the background technique, a masking layer such as patterned photoresist layer 80 is formed covering the active area 40 where the PFET 14 will be formed while exposing the area where the NFET 12 will be formed. Wet etching is then performed such that the spacer 72 is made thinner for the NFET 12 than the spacer 70 as exists in the PFET area 14.
A problem of this background technique is that the wet etch process used to pattern the gate sidewall spacer is not very precise. Wet etching is usually isotropic or substantially isotropic in character, such that it tends to proceed uniformly in different directions. Because of this, wet etching tends to undercut material under a masking layer. However, such effect reduces over the distance from the edge of the masking layer 80. As a result, a tapered region 75 results in which the spacer has width between that of spacer 70 and spacer 72 in the respective PFET and NFET regions. A disadvantage of the spacers 70, 72 having a tapered region 75 between them is reduced process window. As shown in FIG. 1A, the distance 52 between the edge of the NFET active area 42 and the tapered region 75 is rather small. This small distance 52 represents the overlay tolerance between the various lithographic processes used to define the locations of the active areas and the masking layer 80, among others. As is well understood, small overlay tolerance can lead to problems in manufacturing yields. While one way to increase the overlay tolerance would be to increase the distance between the active areas 40 and 42, such would be undesirable as it would lead to a less compact circuit and longer gate conductor patterns having an increased RC (resistance-capacitance) time constant.
Therefore, it would be desirable to provide a process for defining the widths of gate sidewall spacers of respective FETs of an integrated circuit which provides increased overlay tolerance.